Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog a

Search list

[VHDL-FPGA-Verilog] verilog-hdl

Description: verilog—hdl教程135例大量的数字点电路例子-verilog-hdl Tutorial 135 cases of a large number of digital point circuit example
Platform: | Size: 168960 | Author: awake | Hits:

[VHDL-FPGA-Verilog] Verilog[lattice]

Description: 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.-This is a very good value Verilog tutorial, I am going to be intended to greatly therefore, contribute to the U.S. again, I hope everybody help.
Platform: | Size: 143360 | Author: ixia | Hits:

[Crack Hack] verilog

Description: 用于aes128加密的扩展密钥算法，比较详细-For the expansion of key aes128 encryption algorithm, a more detailed
Platform: | Size: 11264 | Author: zsh | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个用verilog语言设计的数字频率及的源代码，上传一下，供大家研究 -This is a design using Verilog language and the digital frequency of the source code, upload click for U.S. research
Platform: | Size: 427008 | Author: bbbbbbbb | Hits:

[VHDL-FPGA-Verilog] FIFO_Buffer(verilog)

Description: 这是一个FIFO_Buffer的verilog代码.-This is a FIFO_Buffer the Verilog code.
Platform: | Size: 71680 | Author: 郑海伟 | Hits:

[VHDL-FPGA-Verilog] example.verilog.pdf

Description: 关于verilog的大量例子，通过这些例子的掌握，可以设计任何常用的程序。-On a large number of examples of Verilog, through mastery of these examples, you can design any commonly used procedures.
Platform: | Size: 113664 | Author: 李里 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子-Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of
Platform: | Size: 159744 | Author: luojinwen | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[Other] 11912930snug06_cohen_sri_aji1.tar

Description: system verilog 的好例子 system verilog 的好例子-system verilog a good example of a good example of system verilog
Platform: | Size: 346112 | Author: ah | Hits:

[Other] ref-sdr-sdram-verilog

Description: sdram控制器的开发程序，还有文档，可以参考以下-SDRAM controller development process, there is a document, you can refer to the following
Platform: | Size: 776192 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 8051core-Verilog 用Verilog写的8051内核 很不错的-8051core-Verilog with Verilog cores 8051 wrote a very good
Platform: | Size: 299008 | Author: awake | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
Platform: | Size: 113664 | Author: 张席龙 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog 经典实例，完整源码与大家分享-Verilog classic example of a complete source to share with you
Platform: | Size: 3658752 | Author: 王之希 | Hits:

[Crack Hack] A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS

Description: A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC校验理论与实践的经典教程，Ross写的。-A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC checksum of the classic theory and practice tutorials, Ross wrote.
Platform: | Size: 184320 | Author: haoz | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
Platform: | Size: 8943616 | Author: 陈江 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
Platform: | Size: 771072 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: VHDL实现的红绿灯控制系统,简单而又实用。-VHDL to achieve traffic light control system, a simple and practical.
Platform: | Size: 123904 | Author: 卢鑫 | Hits:

[Other] Verilog

Description: verilog的简要教程 基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以 是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:
« 1 2 34 5 6 7 8 9 10 ... 50 »

CodeBus www.codebus.net